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3.11.4
Clock Frequency Division
For each type of internal operation clock signal, the divide ratio relative to the base
clock frequency can be set. This feature allows the optimum operating frequency to be
set for each circuit.
The divide ratio is set by the combination of the DIVR0 (base clock frequency division setting register 0)
and DIVR1 (base clock frequency division setting register 1). Each of the registers has four setting bits for
each type of clock signal. The divide ratio of a clock signal relative to the base clock frequency is
expressed as "the register value for that signal + 1". Even though a divide ratio setting is an odd number,
the duty ratio is always 50%.
When the divide ratio setting is changed, the new setting takes effect at the next rise of the clock signal.
Even when an operation initialization reset (RST) occurs, the divide ratio setting is not initialized but
remains unchanged. It is initialized only at a setting initialization reset (INIT). Before changing the source
clock to a faster one from the initial state, be sure to set the divide ratio.
Note:
If you set a combination of the source clock, main PLL multiplier, and divide ratio, which results in a
frequency higher than the maximum operating frequency, the operation of the device is not
guaranteed. Use meticulous care not to set such a combination of values (in particular, do not select
the source clock and change settings in wrong order).
CHAPTER 3 CPU AND CONTROL UNITS
75
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