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CHAPTER 9 PPG (Programmable Pulse Generator)
■ PPG Output Operation
PPG activates this block and starts counting when the bits of each channel on the TRG register (PPG
activation register) are set to "1". After operation starts, the count operation is stopped when each channel
bit of TRG register is set to "0". After having stopped, the pulse output holds "L" level.
Do not set the PPG channel as the operating state, with the prescaler channel as the stopped state, in the 8-
bit prescaler + 8-bit PPG mode and the 16-bit prescaler + 16-bit PPG mode.
In the 16-bit PPG mode, control the start and stop for PENn of each channel on TRG register
simultaneously (n = 0 to 15).
PPG output operation is explained below.
In PPG operation, the pulse wave with any frequency/duty ratio (the ratio between "H" level period and "L"
level period in pulse wave) is outputted continuously. If the pulse wave output is started, PPG will not stop
it before operation stop is set.
Figure 9.4-1 shows the output waveform of PPG operation.
PENn
Output pin
PPG
n = 0 to 15
■ Relation between Reload Value and Pulse Width
The pulse width to be outputted is the value that multiplies the cycle of the count clock by the value in the
reload register plus 1. Note that the pulse width will be one cycle of the count clock when the reload
register value is set to "00
at operating the 16-bit PPG. Furthermore, the pulse width will be 256 cycles of the count clock when the
reload register value is set to "FF
when the reload register value is set to "FFFF
The equations for calculating the pulse width are shown below:
178
Figure 9.4-1 Output Waveform of PPG Output Operation
Start operation
by PENn
(from "L" side)
T × (L+1)
Start
" at operating the 8-bit PPG and when the reload register value is set to "0000
H
" at operating the 8-bit PPG and will be 65536 cycles of the count clock
H
Pl = T × (L + 1)
Ph = T × (H + 1)
L: PRLL value
T × (H+1)
H: PRLH value
T: Machine clock
Input from timebase counter
" at operating the 16-bit PPG.
H
L: PRLL value
{
H: PRLH value
T: input clock cycle
Ph: high pulse width
Pl: low pulse width
or
(by clock select of PPGC)
"
H
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