Fujitsu MB91260B Series Hardware Manual page 326

[bit5] FRE (FRaming Error):
This bit, which is an interrupt request flag, is set when a framing error occurs during reception.
To clear the flag when it has been set, write "0" to the REC bit of the SCR register.
If the FRE bit is set, the SIDR data becomes invalid.
0: No framing error has occurred. [Initial value]
1: A framing error has occurred.
Notes:
• Switch the internal and external baud rate clocks using bit3 of the serial mode register only while
the UART is stopped, since the switching takes effect immediately after writing.
• Bit3 of the serial mode register is write-only.
[bit4] RDRF (Receiver Data Register Full):
This bit, which is an interrupt request flag, indicates that the SIDR register has receive data.
This bit is set when receive data is loaded into the SIDR register. It is automatically cleared when the data
is read from the SIDR register.
0: No receive data exists. [Initial value]
1: Receive data exists.
[bit3] TDRE (Transmitter Data Register Empty):
This bit, which is an interrupt request flag, indicates whether send data can be written to SODR register.
This bit is cleared when send data is written to the SODR register. It is set again when the written data is
loaded into the send shifter and begins to be transferred, indicating that the next send data can be written.
0: Disables writing of send data.
1: Enables writing of send data. [Initial value]
[bit2] BDS (Bit Direction Select)
This bit selects the transfer direction.
0: Sends starting from the least significant bit (LSB). [Initial value]
1: Sends starting from the most significant bit (MSB).
Note:
Because the high-order and low-order data are switched when the serial data register is written or
read, the data will become invalid if the bit is rewritten after data is written to the SODR register.
If the SODR register and BDS are rewritten at the same time using halfwords (16 bits), data will be
written to the SODR register based on the BDS value before rewriting.
CHAPTER 13 UART
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