Fujitsu MB91260B Series Hardware Manual page 262

■ 16-bit Dead Timer Control Register (DTCR1)
16-bit dead timer control register
Bit7 Bit6
DMOD1 GTEN3
R/W R/W
R/W: Read/Write
: Initial value
Bit5 Bit4 Bit3
GTEN2 TMIF1 TMIE1
R/W R/W R/W
TMD5 TMD4 TMD3
0
0
0
1
1
TMIE1
0
1
TMIF1
0
1
GTEN2
0
1
GTEN3
0
1
DMOD1
0
1
CHAPTER 11 MULTIFUNCTIONAL TIMER
Bit2 Bit1 Bit0
TMD5 TMD4 TMD3
R/W R/W R/W
0 0 Waveform generator stops.
0 1 PPG0 timer outputs pulse while RT signal is at "H".
Rising edge of each RT signal becomes trigger,
and 16-bit dead timer stars. The PPG timer outputs
0
1
pulse until the 16-bit dead timer stops. (timer mode)
Non-overlap signal is generated by the RT
0
0
signal. (dead time timer mode)
Non-overlap signal is generated by PPG0
1
1
timers. (dead time timer mode)
Other
Interrupt request enable bit, software trigger bit
Interrupt is not generated even though underflow is generated
in 16-bit dead timer.
Interrupt is generated when underflow is generated in 16-bit
dead timer.
Interrupt request flag bit
Read
Underflow of counter is not
detected.
Underflow of counter is
detected.
GATE signal control bit 2
The GATE signal is not controlled by RT2. (asynchronous mode)
The GATE signal is controlled by RT2. (synchronous mode)
GATE signal control bit 3
The GATE signal is not controlled by RT3. (asynchronous mode)
The GATE signal is controlled by RT3. (synchronous mode)
Output polarity control bit
Normal polarity output
Reverse polarity output
DTCR1
Address: 0000C5
H
Initial value: 00000000
Operation mode bit
Disable
Write
This bit is cleared.
No effect on this bit.
B
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