Peripheral Circuits In The Clock Control Unit - Fujitsu MB91260B Series Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.11.7

Peripheral Circuits in the Clock Control Unit

This section describes peripheral circuits in the clock control unit.
■ Timebase Counter
The clock control unit incorporates a 26-bit timebase counter operating with the internal base clock.
The timebase counter is used for measurement of the oscillation stabilization wait time (detailed in
"■ Oscillation stabilization wait time" in Section 3.10 "Reset (Device Initialization)") and for the following
applications as well:
- Watchdog timer
The watchdog timer for detecting system runaway performs measurement using the bit output of the
timebase counter.
- Timebase timer
The timebase timer generates an interval interrupt using the timebase counter output.
These functions are described below:
●
Watchdog timer
The watchdog timer is a runaway detection timer using the timebase counter output. If a program runs
out of control, preventing the watchdog reset defer function from being executed within the set interval,
for example, the watchdog timer generates a setting initialization reset (INIT) request for a watchdog
reset.
[Activating the watchdog timer and setting its time interval]
The watchdog timer is activated upon the first write to the RSRR (reset source register/watchdog timer
control register) after a reset (RST). At this time, the WT1 and WT0 bits (bit9 and bit8) are used to set
the time interval for the watchdog timer. Only the time interval set at the first write to the RSRR takes
effect; the settings made at any further writes are ignored.
[Deferring the generation of a watchdog reset]
Once the watchdog timer is activated, "A5
the CTBR (timebase counter clear register) by a program. This initializes the watchdog reset generation
flag.
[Generating a watchdog reset]
The watchdog reset generation flag is set at the falling edge of the timebase counter output during the
set interval. If the flag has been set when the second falling edge is detected, a setting initialization
reset (INIT) request is generated for a watchdog reset.
[Stopping the watchdog timer]
Once the watchdog timer is activated, it cannot be stopped until an operation initialization reset (RST)
occurs.
In the following states in which an operation initialization reset (RST) occurs, the watchdog timer stops
and will not function until it is programmed to be reactivated.
90
" and "5A " must be written, in this order, periodically to
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