Fujitsu MB91260B Series Hardware Manual page 257

CHAPTER 11 MULTIFUNCTIONAL TIMER
■ PPG Control Register, Lower Byte (PICSL01)
Output control register (Lower)
Bit7 Bit6
ICP1 ICP0
R/W R/W
R/W: Read/Write
: Initial value
242
Bit5 Bit4 Bit3
ICE1 ICE0 EG11
R/W R/W R/W
EG01 EG00
0
0
1
1
EG11 EG10
0
0
1
1
ICE0
0
1
ICE1
0
1
ICP0
0
1
ICP1
0
1
Bit2 Bit1 Bit0
EG10 EG01 EG00
R/W R/W R/W
Edge selection bit (input capture 0)
0 Edge is not detected (stop)
1 Rising edge is detected.
0 Falling edge is detected.
1 Both edge are detected.
Edge selection bit (input capture 1)
0 Edge is not detected (stop)
1 Rising edge is detected.
0 Falling edge is detected.
1 Both edge are detected.
Interrupt request enable bit (input capture 0)
Disable interrupt request
Enable interrupt request
Interrupt request enable bit (input capture 1)
Disable interrupt request
Enable interrupt request
Interrupt request flag bit (input capture 0)
Read
Valid edge is not detected.
Valid edge is detected.
Interrupt request flag bit (input capture 1)
Read
Valid edge is not detected.
Valid edge is detected.
PICSL01
Address: 0000B5
H
Initial value: 00000000
Write
This bit is cleared.
No effect on this bit.
Write
This bit is cleared.
No effect on this bit.
B