Operation - Fujitsu MB91260B Series Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS
3.8.6

Operation

This section explains the operation of EIT.
The "PC" (program counter) as the source of transfer hereafter indicates the address of
an instruction where each EIT source has been detected. The "next instruction's
address" indicates as follows depending on the EIT-detected instruction:
• LDI: 32 → PC value + 6
• LDI: 20, COPOP, COPLD, COPST, COPSV → PC value + 4
• Else → PC value + 2
Parentheses ( ) in [Processing] below enclose the address specified by the relevant
register.
■ Operation of User Interrupt/NMI
When a user interrupt or user NMI interrupt request is issued, the acceptance of the request is determined in
the following order:
[Determining the acceptance of interrupt request]
1. The interrupt levels of requests issued simultaneously are compared and the request of the highest level
(smallest value) is selected.
The level of a maskable interrupt is compared with the value held in the corresponding ICR and that of
an NMI is compared with a predetermined constant.
2. If two or more interrupt requests of the same level are issued, the interrupt request of the smallest
interrupt number is selected.
3. The selected interrupt request is masked and rejected if its interrupt level is equal to or greater than the
level mask value.
When the interrupt level is smaller than the level mask value, go to step 4. below.
4. If the selected interrupt request is maskable, the interrupt request is masked and rejected when the I-flag
is "0". When the I-flag is "1", go to step step 5. below.
If the selected interrupt request is an NMI, go to step step 5. below regardless of the value in the I-flag.
5. When the above conditions are satisfied, the interrupt request is accepted at a break of instruction
processing.
If a user interrupt/NMI request is received upon detection of an EIT request, the CPU performs the
following steps using the interrupt number corresponding to the accepted interrupt request.
[Processing]
1. SSP-4
2. PS
3. SSP-4
4. Next instruction's address
5. Interrupt level of accepted request → ILM
6. "0"
7. (TBR + vector offset of accepted interrupt request) → PC
The CPU tries to detect a new EIT before executing the first instruction in the handler upon completion of
the interrupt sequence. If an acceptable EIT has occurred, the CPU enters the EIT servicing sequence.
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→ SSP
→ (SSP)
→ SSP
→ (SSP)
→ S-flag