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16.2
Register Details Explanation
This section explains the register configuration and function for using DMAC.
■ Notes on Setting Register
Some bits in the DMAC may only be set when the DMA is halted. If set during operation (during transfer),
correct operation cannot be guaranteed.
An asterisk "*" indicates bits that will affect operation if set during DMAC transfer. Only modify this bit
when the DMAC transfer is halted (set to the disabled or paused state). Values set while DMA transfer is
disabled (DMACR: DMAE=0 or DMACA: DENB=0) become active when DMA is re-enabled.
Values set while DMA transfer is paused (DMACR: DMAH(3:0)≠ 0000
active when DMA is restarted.
■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Control/Status Registers A
[DMACA0 to DMACA4]
These registers control the operation of each DMAC channel. A separate register is provided for each
channel.
The function of each bit is as follows.
bit
31
30
29
DENB PAUS STRG
bit
15
14
13
[bit31] DENB (Dma ENaBle): DMA Operation Enable Bit
Enables or disables DMA transfer for each transfer channel.
Once a channel is enabled, DMA transfer starts when a transfer request is received.
All transfer requests for disabled channels are ignored.
This bit goes to "0" when the specified number of transfers has completed for an enabled channel and the
transfer halts.
Although writing "0" to this bit forcibly halts DMA, always use the PUAS bits (DMACA: bit30) to pause
DMA before forcibly halting (writing "0"). If DMA transfer is forcibly halted without pausing, the DMA
transfer halts but the validity of the transferred data is not guaranteed. Use the DSS(2:0) bits (DMACB:
bit18 to bit16) to check whether transfer has finished.
DENB
• After a reset or when a halt request is received: Initialized to "0".
• The read / write is possible.
28
27
26
25
24
IS[4:0]
12
11
10
9
8
DTC[15:0]
0
Corresponding channel DMA is disabled to operate [initial value].
1
Corresponding channel DMA is enabled to operate.
CHAPTER 16 DMAC (DMA Controller)
23
22
21
20
19
-
7
6
5
4
3
(Initial value: 00000000 00000000 00000000 00000000
Function
or DMACA: PAUS=1) become
B
18
17
16
BLK[3:0]
2
1
0
)
B
371
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