Fujitsu MB91260B Series Hardware Manual page 208

■ Count Clock Selection
The count clock of counter can select three types of internal clock sources by setting of PWCSR register
(bit7, bit6: CKS1, CKS0).
Selectable count clocks are as shown below.
The clock generated by dividing the machine clock by 4 is selected for the initial value after a reset.
Be sure to select the count clock before the counter starts.
■ Selects Operation Mode
The PWCSR setting is used to select each operation/measurement mode.
• Operation mode setting:
• Measurement mode setting:PWCSR bit3: SC
The selection of operation modes by the combination of the mode selecting bits is listed below.
↑ or ↓ to ↑ or ↓
Measurement between all edges
Measurement at cycle of
dividing frequency
(1-frequency division to
256-frequency division)
↑ to ↑ Rising-to-rising cycle
Pulse width
measurement
measurement
"H" pulse width measurement
"L" pulse width measurement
↓ to ↓ Falling-to-falling cycle
measurement
All edge-to-edge measurement-single measurement mode is selected for the initial value after a reset.
Be sure to select the activation mode before the counter starts.
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
PWCSR
CKS1, CKS0
00
Machine clock 4-divided [initial value]
B
01
Machine clock 16-divided
B
10 Machine clock 32-divided
B
PWCSR bit2 to bit0: MOD2, MOD1, MOD0
(for example, selecting a pulse width count mode, or determining a
measurement edge)
(selecting a single/continuous measurement)
Operating Mode
Single measurement: Buffer invalidity
Continuous measurement: Buffer effective
Single measurement: Buffer invalidity
Continuous measurement: Buffer effective
Single measurement: Buffer invalidity
Continuous measurement: Buffer effective
↑ to ↓
Single measurement: Buffer invalidity
Continuous measurement: Buffer effective
↓ to ↑
Single measurement: Buffer invalidity
Continuous measurement: Buffer effective
Single measurement: Buffer invalidity
Continuous measurement: Buffer effective
Setting disabled
Selecting Internal Count Clock
SC
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MOD2 MOD1 MOD0
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
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