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APPENDIX E Instruction Lists
Appendix Table E-8 Memory Load
Mnemonic
LD @Rj, Ri
LD @(R13,Rj), Ri
LD @(R14,disp10),Ri
LD @(R15,udisp6),Ri
LD @R15+, Ri
LD @R15+, Rs
LD @R15+, PS
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
*1: In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
disp10/4->o8, disp9/2->o8, disp8->o8, disp10, disp9, and disp8 have a sign, udisp6/4->o4 udisp6 has no sign.
Appendix Table E-9 Memory Store
Mnemonic
ST Ri,@Rj
ST Ri,@(R13,Rj)
ST Ri,@(R14,disp10)
ST Ri,@(R15,udisp6)
ST Ri,@-R15
ST Rs,@-R15
ST PS,@-R15
STH Ri,@Rj
STH Ri,@(R13,Rj)
STH Ri,@(R14,disp9)
STB Ri,@Rj
STB Ri,@(R13,Rj)
STB Ri,@(R14,disp8)
*1: In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:
disp10/4->o8, disp9/2->o8, disp8->o8, disp10, disp9, and disp8 have a sign, udisp6/4->o4 udisp6 has no sign.
Appendix Table E-10 Register-to-Register Transfer
Mnemonic
MOV Rj, Ri
MOV Rs, Ri
MOV Ri, Rs
MOV PS, Ri
MOV Ri, PS
*1:
Special register Rs: TBR, RP, USP, SSP, MDH, and MDL
466
Type
OP
CYCLE
A
04
b
A
00
b
B
2
b
C
03
b
E
07-0
b
E
07-8
b
E
07-9
1+a+b
A
05
b
A
01
b
B
4
b
A
06
b
A
02
b
B
6
b
Type
OP
CYCLE
A
14
a
A
10
a
B
3
a
C
13
a
E
17-0
a
E
17-8
a
E
17-9
a
A
15
a
A
11
a
B
5
a
A
16
a
A
12
a
B
7
a
Type
OP
CYCLE
A
8B
1
A
B7
1
E
B3
1
E
17-1
1
E
07-1
c
NZVC
Operation
----
(Rj)->Ri
----
(R13+Rj)->Ri
----
(R14+disp10)->Ri
----
(R15+udisp6)->Ri
----
(R15)->Ri,R15+=4
----
(R15)->Rs,R15+=4
CCCC
(R15)->PS, R15+=4
----
(Rj)->Ri
----
(R13+Rj)->Ri
----
(R14+disp9)->Ri
----
(Rj)->Ri
----
(R13+Rj)->Ri
----
(R14+disp8)->Ri
NZVC
Operation
----
Ri->(Rj)
----
Ri->(R13+Rj)
----
Ri->(R14+disp10)
----
Ri->(R15+udisp6)
----
R15-=4,Ri->(R15)
----
R15-=4, Rs->(R15)
----
R15-=4, PS->(R15)
----
Ri->(Rj)
----
Ri->(R13+Rj)
----
Ri->(R14+disp9)
----
Ri->(Rj)
----
Ri->(R13+Rj)
----
Ri->(R14+disp8)
NZVC
Operation
----
Rj -> Ri
----
Rs -> Ri
----
Ri -> Rs
----
PS -> Ri
CCCC
Ri -> PS
Remarks
Rs: Special register
Zero extension
Zero extension
Zero extension
Zero extension
Zero extension
Zero extension
Remarks
Word
Word
Word
Rs Special register
Halfword
Halfword
Halfword
Byte
Byte
Byte
Remarks
Transfer between general-
purpose registers
Rs: Special register
Rs: Special register
*1
*1
*1
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