Table of Contents
Advertisement
CHAPTER 16 DMAC (DMA Controller)
■ DMAC Interrupt Control
Independent of peripheral interrupts that become transfer requests, interrupts can also be outputted for each
DMAC channel.
• Transfer end interrupt: Occurs only when operation ends normally.
• Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral). All of these
interrupts are outputted according to the meaning of the end code.
An interrupt request can be cleared by writing "000
Be sure to clear the end code by writing "000
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not
cleared and is retained until a new end code is written when the next transfer ends.
Since only one end source can be displayed in an end code, the result after considering the order of priority
is displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to
the displayed end code.
The following shows the priority for displaying end codes (in order of decreasing priority):
• Reset
• Clear by writing "000
• Peripheral stop request
• Successful completion
• Channel selection and control
■ DMA Transfer in Sleep Mode
The DMAC can also operate in sleep mode.
If you anticipate operations during sleep mode, note the following:
• Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is
entered.
• The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start
source, interrupts must be disabled by the interrupt controller.
Similarly, if you do not want to release sleep mode with a DMAC end interrupt, disable DMAC end
interrupts.
396
" before restarting.
B
".
B
" to DSS2 to DSS0 (end code) of DMACS.
B
Advertisement
Table of Contents
