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Appendix Table E-5 Multiplication and Division
Mnemonic
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
*DIV Ri
*1
*DIVU Ri
*2
Appendix Table E-6 Shift
Mnemonic
LSL Rj, Ri
*LSL #u5, Ri(u5:0 to 31)
LSL #u4, Ri
LSL2 #u4, Ri
LSR Rj, Ri
*LSR #u5, Ri(u5:0 to 31)
LSR #u4, Ri
LSR2 #u4, Ri
ASR Rj, Ri
*ASR #u5, Ri (u5:0 to 31)
ASR #u4, Ri
ASR2 #u4, Ri
Appendix Table E-7 Immediate Value Set/16-Bit/32-Bit Immediate Value Transfer Instruction
Mnemonic
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
*LDI # {i8|i20|i32} ,Ri
*1:
DIV0S, DIV1 x 32, DIV2, DIV3, and DIV4S are generated. The instruction code length becomes 72 bytes.
*2:
DIV0U and DIV1 x 32 are generated. The instruction code length becomes 66 bytes.
*3:
If the immediate value is an absolute value, i8, i20, or i32 is selected automatically by the assembler.
If immediate value contains a relative value or an external reference symbol, i32 is selected.
Type
OP
CYCLE
A
AF
5
A
AB
5
A
BF
3
A
BB
3
E
97-4
1
E
97-5
1
E
97-6
d
E
97-7
1
E
9F-6
1
E
9F-7
1
36
Type
OP
CYCLE
A
B6
C'
B4
C
B4
C
B5
A
B2
C'
B0
C
B0
C
B1
A
BA
C'
B8
C
B8
C
B9
Type
OP
CYCLE
E
9F-8
3
C
9B
2
B
C0
1
*3
NZVC
Operation
CCC-
Ri * Rj -> MDH, MDL
CCC-
Ri * Rj -> MDH, MDL
CC--
Ri * Rj -> MDL
CC--
Ri * Rj -> MDL
----
----
-C-C
-C-C
----
----
-C-C
MDL / Ri -> MDL , MDL % Ri -> MDH
-C-C
MDL / Ri -> MDL , MDL % Ri -> MDH
NZVC
1
CC-C
Ri << Rj -> Ri
1
CC-C
Ri << u5 -> Ri
1
CC-C
Ri << u4 -> Ri
1
CC-C
Ri <<(u4+16) -> Ri
1
CC-C
Ri >> Rj -> Ri
1
CC-C
Ri >> u5 -> Ri
1
CC-C
Ri >> u4 -> Ri
1
CC-C
Ri >>(u4+16) -> Ri
1
CC-C
Ri >> Rj -> Ri
1
CC-C
Ri >> u5 -> Ri
1
CC-C
Ri >> u4 -> Ri
1
CC-C
Ri >>(u4+16) -> Ri
NZVC
Operation
----
i32 -> Ri
----
i20 -> Ri
----
i8 -> Ri
{i8 | i20 | i32} -> Ri
APPENDIX E Instruction Lists
Remarks
32bit*32bit=64bit
No sign
16bit*16bit=32bit
No sign
Step operation
32bit/32bit=32bit
Operation
Logical shift
Logical shift
Arithmetic shift
Remarks
High-order 12 bits are zero-extended.
High-order 24 bits are zero-extended.
Remarks
465
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