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• UART (full duplex, double buffering): 3 channels
Choice of enabling/disabling parity
Choice of clock asynchronous (start-stop) or synchronous communication
Dedicated baud rate timer (U-TIMER) integrated for each channel
Capable of using an external clock as a transfer clock
Detection of parity, frame, and overrun errors
• 8/16-bit PPG timer: 16 channels (in 8-bit mode) / 8 channels (in 16-bit mode)
• 16-bit reload timer: 3 channels (cascade mode available, with no output of reload timer 0)
• 16-bit free-running timer: 1 channel
• 16-bit PWC timer: 2 channels
• Input capture unit: 4 channels (interlocking with the free-running timer)
• Output compare unit: 6 channels (interlocking with the free-running timer)
• Waveform generator
Capable of generating various waveforms using the output compare unit's output, 16-bit PPG timer 0,
and 16-bit dead timer.
• Multiplier-accumulator
RAM: Instruction RAM 256 × 16 bits
Executes a multiply-accumulate operation (16 bits × 16 bits + 40 bits) in one instruction cycle.
Extracts the operation result by rounding from 40 bits to 16 bits.
• DMAC (DMA Controller): 5 channels
Capable of starting transfer of built-in peripheral interrupts by means of software
• Watchdog timer
• Low-power consumption modes
Sleep and stop modes
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Others
• Package: QFP-100, LQFP-100
• CMOS 0.35 µm technology
• Single power supply [Vcc = 4.0 V to 5.5 V]
XRAM 64 × 16 bits
YRAM 64 ×16 bits
CHAPTER 1 OVERVIEW
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