Fujitsu MB91260B Series Hardware Manual page 272

■ 16-bit Output Compare Interrupt
See Table 11.5-2 for 16-bit output compare interrupt control bits and interrupt causes.
Table 11.5-2 16-bit Output Compare 0 to 5 Interrupt Control Bits and Interrupt Causes
Interrupt request flag bit
Interrupt request enable bit
Interrupt cause
When the 16-bit free-run timer value and output compare register (OCCPH0 to OCCPH5, OCCPL0 to
OCCPL5) match, the compare control register low-order (OCSL0, OCSL2, and OCSL4) IOP 1 and 0: bit7
and bit6 are set to "1". When interrupt requests are enabled in this state (OCSL0, OCSL2, and OCSL4
register IOE1 and IOE0: bit5, bit4 = 11
16-bit Output Compare 0, 1 16-bit Output Compare 2, 3 16-bit Output Compare 4, 5
IOP1, IOP0 (bit7, bit6) of
lower compare control
register (OCSL0)
IOE1, IOE0 (bit5, bit4) of
lower compare control
register (OCSL0)
The 16-bit free-run timer
value and output compare
register (OCCPH0,
OCCPH1, OCCPL0,
OCCPL1) match.
B
CHAPTER 11 MULTIFUNCTIONAL TIMER
IOP1, IOP0 (bit7, bit6) of
lower compare control
register (OCSL2)
IOE1, IOE0 (bit5, bit4) of
lower compare control
register (OCSL2)
The 16-bit free-run timer
value and output compare
register (OCCPH2,
OCCPH3, OCCPL2,
OCCPL3) match.
), interrupt requests are outputted to the interrupt controller.
IOP1, IOP0 (bit7, bit6) of
lower compare control
register (OCSL4)
IOE1, IOE0 (bit5, bit4) of
lower compare control
register (OCSL4)
The 16-bit free-run timer
value and output compare
register (OCCPH4,
OCCPH5, OCCPL4,
OCCPL5) match.
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