Fujitsu MB91260B Series Hardware Manual page 501

INDEX
Microcontroller Programmer
System Configuration of AF200 Flash Microcontroller
Programmer (Yokogawa Digital Computer
Corporation).....................................................435
MOD
Operation of 16-bit Output Compare
(Inverted Mode,MOD1x=0) ............................267
Operation of 16-bit Output Compare
(Set/Reset Mode,MOD15 to MOD10=1)
.........................................................................271
Mode
Asynchronous (Start-stop Synchronization) Mode
.........................................................................314
Mode Setting......................................................................62
Returning from Standby Mode (Stop or Sleep Mode)
.........................................................................125
mon911
Debugger (sim911,eml911,mon911) ...............................459
Monitor Output
Variable Monitor Output .................................................361
Multifunctional Timer
Block Diagram of Multifunctional Timer........................206
Configuration of Multifunctional Timer..........................204
Operation of Multifunctional Timer ................................260
Pins of Multifunctional Timer .........................................212
Multiplier
PLL Multiplier ...................................................................71
Wait Times after the PLL Multiplier is Changed ..............72
N
NMI
NMI..................................................................................136
NMI (Non Maskable Interrupt)........................................124
Operation of User Interrupt/NMI.......................................58
NMI Level
Interrupt/NMI Level Masking ...........................................50
Noise Cancel
DTTI Pin Noise Cancel Feature.......................................290
Non Maskable Interrupt
NMI (Non Maskable Interrupt)........................................124
Note
Note..................................................................................201
Notes ................................................................................162
Notes on Setting Register ................................................371
O
OCCPBH
Output Compare Buffer Register (OCCPBH: OCCPBH0 to
OCCPBH5,OCCPBL: OCCPBL0 to OCCPBL5)
.........................................................................227
OCCPBL
Output Compare Buffer Register (OCCPBH: OCCPBH0 to
OCCPBH5,OCCPBL: OCCPBL0 to OCCPBL5)
.........................................................................227
486
OCCPH
Output Compare Register (OCCPH: OCCPH0 to
OCCPH5,OCCPL: OCCPL0 to OCCPL5)
......................................................................... 228
OCCPL
Output Compare Register (OCCPH: OCCPH0 to
OCCPH5,OCCPL: OCCPL0 to OCCPL5)
......................................................................... 228
OCMOD
Compare Mode Control Register (OCMOD).................. 234
OCSH
Compare Control Register,Upper Byte
(OCSH1,OCSH3,OCSH5) .............................. 229
OCSL
Compare Control Register,Lower Byte
(OCSL0,OCSL2,OCSL4) ............................... 232
Operating Mode
Operating Mode ......................................................177
Operating Modes............................................................. 313
Operating States
Operating States of the Counter ...................................... 161
Operation
Overview of Operation............................................177
Operation Mode
Operation Modes............................................................... 62
Selects Operation Mode .................................................. 193
Operation Start
Operation Start ................................................................ 393
Ordering
Bit Ordering ...................................................................... 40
Byte Ordering.................................................................... 40
Oscillation Clock
Oscillation Clock Frequency........................................... 435
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time.................................. 67
Output Compare
16-bit Output Compare and Free-run Timer Operation
......................................................................... 273
16-bit Output Compare Interrupt .................................... 257
16-bit Output Compare Register ..................................... 214
16-bit Output Compare Timing....................................... 272
Notes on Using 16-bit Output Compare.......................... 292
Operation of 16-bit Output Compare
(Inverted Mode,MOD1x=0)............................ 267
Operation of 16-bit Output Compare
(Set/Reset Mode,MOD15 to MOD10=1)
......................................................................... 271
Program Example of 16-bit Output Compare ................. 295
Output Compare Buffer Register
Output Compare Buffer Register (OCCPBH: OCCPBH0 to
OCCPBH5,OCCPBL: OCCPBL0 to OCCPBL5)
......................................................................... 227
Output Compare Register
Output Compare Register (OCCPH: OCCPH0 to
OCCPH5,OCCPL: OCCPL0 to OCCPL5)
......................................................................... 228
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359
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385