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CHAPTER 3 CPU AND CONTROL UNITS
5. "00100
6. "0"
7. (TBR + 3CC
If the T-flag is set to enable the step trace trap function, user NMIs and user interrupts are disabled. In
addition, the INTE instruction no longer generates an EIT.
A trap is generated at the execution of the instruction immediately after setting the T-flag.
■ Processing of Undefined Instruction Exception
If an instruction is found undefined during instruction decoding, an undefined instruction exception occurs.
[Undefined instruction exception detection conditions]
• Instruction found undefined during instruction decoding
• Placed outside the delay slot (not immediately after the delayed branch instruction)
• If the above conditions are satisfied, an undefined instruction exception occurs, causing a break.
[Processing]
1. SSP - 4
2. PS
3. SSP - 4
4. PC
5. "0"
6. (TBR + 3C4
The PC saves the address of the instruction where the undefined instruction exception was detected.
■ Coprocessor Absence Trap
A coprocessor absence trap occurs if a coprocessor instruction which attempts to use an absent coprocessor
is executed.
[Processing]
1. SSP - 4
2. PS
3. SSP - 4
4. Next instruction's address → (SSP)
5. "0"
6. (TBR + 3E0
60
→ ILM
"
B
→ S-flag
→ PC
)
H
→ SSP
→ (SSP)
→ SSP
→ (SSP)
→ S-flag
→ PC
)
H
→ SSP
→ (SSP)
→ SSP
→ S-flag
→ PC
)
H
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