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CHAPTER 3 CPU AND CONTROL UNITS
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Watchdog reset
When data is written to the RSRR (watchdog timer control register), the watchdog timer is activated. A
watchdog reset request occurs unless A5
performed within the period set by the WT1 and WT0 bits (bit9 and bit8) in the RSRR.
The watchdog reset request is a setting initialization reset (INIT) request. When the request is accepted and
a setting initialization reset (INIT) or operation initialization reset (RST) is generated, the watchdog reset
request is canceled.
When a setting initialization reset (INIT) is generated by a watchdog reset request, the WDOG bit (bit13) in
the RSRR (reset source register) is set.
Note that the oscillation stabilization wait time setting is not initialized when a setting initialization reset
(INIT) is generated by a watchdog reset request. Note also that the oscillation stabilization wait time is not
taken unless main oscillation is stopped during a main run or sub-run.
•
Reset source
•
Cancel source : Occurrence of a setting initialization reset (INIT) or operation initialization reset (RST)
•
Reset level
•
Indication flag : bit13 (WDOG bit)
■ Reset Sequence
When a reset source is eliminated, the device starts executing the reset sequence.
The steps performed in the reset sequence vary with the reset level.
The following describes the steps in the reset sequence for each reset level.
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Reset sequence for setting initialization reset (INIT)
When the setting initialization reset (INIT) request is cleared, the device performs the following steps
sequentially.
Note, however, that the device does not take the oscillation stabilization wait time in step (2) for a
watchdog reset when main oscillation is not stopped during a main run or sub-run.
(1) Cancels the setting initialization reset (INIT) and enters the oscillation stabilization wait state.
(2) Maintains the operation initialization reset (RST) state and the internal clock suspended for the
oscillation stabilization wait time (set by the OS1 and OS0 bits, or bit3 and bit2 in the STCR).
(3) Enters the operation initialization reset (RST) state and starts internal clock operation.
(4) Cancels the operation initialization reset (RST) and enters to the normal operating state.
(5) Reads a mode vector from address "000FFFF8
(6) Writes the mode vector to the MODR (mode register).
(7) Reads a reset vector from address "000FFFFC
(8) Writes the reset vector to the PC (program counter).
(9) Starts program operation from the address shown in the PC (program counter).
66
/5A
H
: Watchdog timer time-out
: Setting initialization reset (INIT)
writing to the CTBR (timebase counter clear register) is
H
".
H
".
H
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