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CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
■ JMP Instruction (Branching Command)
Operation:
Explanation: Branch if condition is satisfied, do not perform any operation if condition is not satisfied.
Word count:
Cycle count:
Operation code:
[bit13] HLT (HLT instruction specifying flag)
Setting this bit causes the multiplication and addition macro to halt program execution after instruction
execution completes.
Clears the RunDSP flag in the DSP-CSR register.
[bit12] SIRQ (INT instruction specifying flag)
Setting this bit generates an interrupt request to the CPU after instruction execution completes.
Sets the IrqDSP flag in the DSP-CSR register.
[bit11] COND (CONDition)
0: Unconditional branch
1: Conditional branch
[bit10 to bit8] UBP2 to UBP0 (condition specification)
Sets the condition to use for the conditional branch. The condition is established if these bits match the
value of the USR2 to USR0 bits in the DSP-CSR register.
These bits must be set to "000
[bit7 to bit0] J-Addr8 (Jump Address)
Address specification for branch destination
366
[when condition is satisfied]
[when condition is not satisfied] DSP-PC ← DSP-PC + 1
1 word (16-bit width)
1 system clock cycle
15
14
13
12
0
0
HLT
SIRQ
" if an unconditional branch is specified.
B
DSP-PC ← J-Addr8
11
10 . . . . . . 8
7 . . . . . . . . . . . 0
COND
UBP
J-Addr8
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