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CHAPTER 3 CPU AND CONTROL UNITS
[Clearing the timebase counter by device state]
All the bits in the timebase counter are cleared to "0" when the device causes a transition to the
following states:
- Stop state
- Setting initialization reset (INIT) state
- Hardware standby state
When the device enters the stop state, in particular, the timebase timer may cause an unintentional
interval interrupt as the timebase counter is used for measurement of oscillation stabilization wait time.
Before setting the stop mode, therefore, disable timebase timer interrupts and stop using the timebase
timer.
When the device enters any other state, an operation initialization reset (RST) occurs and thus timebase
timer interrupts are disabled automatically.
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