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CHAPTER 16 DMAC (DMA Controller)
[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Reload setting for transfer destination address
Controls the reload function for the transfer destination address register in the corresponding channel.
When reloading is enabled by this bit, the transfer destination address register is returned to its initial value
when transfer completes.
Other details and functions are the same as described for bit22:SADR.
DADR
• Initialized to "0" when resetting.
• The read / write is possible.
[bit20] ERIE (ERror Interrupt Enable)* : Error interrupt output enabled
This bit controls whether to generate an interrupt when transfer ends if an error occurred. The nature of the
error is indicated by bits DSS2 to DSS0. Note that this interrupt is not generated by all DMA termination
cause. It is generated for specific cause only (see the explanation for bits DSS2 to DSS0).
ERIE
• Initialized to "0" when resetting.
• The read / write is possible.
[bit19] EDIE (EnD Interrupt Enable) *: Enable end interrupt output
Controls whether to output an interrupt when transfer ends normally.
EDIE
• Initialized to "0" when resetting.
• The read / write is possible.
378
0
Transfer destination address register is disabled to reload (initial value).
1
Transfer destination address register is enabled to reload.
0
Error interrupt request output is disabled (initial value).
1
Error interrupt request output is enabled.
0
End interrupt request output is disabled (initial value).
1
End interrupt request output is enabled.
register
Function
Function
Function
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