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CHAPTER 3 CPU AND CONTROL UNITS
[bit1] V: Overflow flag
This flag indicates whether an operand using the operation regarded as an integer represented in two's
complement has resulted in an overflow.
Value
0
1
The initial state after a reset is indeterminate.
[bit0] C: Carry flag
This flag indicates whether an operation has generated a carry or borrow from the MSB.
Value
0
1
The initial state after a reset is indeterminate.
●
SCR (System Condition code Register)
[bit10, bit9] D1, D0: Step division flag
This flag holds intermediate data during execution of step division.
Do not update the content of this flag during execution of the division process.
To execute another process during execution of step division, save and return the values in the PS register
so that the step division can be resumed correctly.
The initial state after a reset is indeterminate.
The flag is set by executing the DIV0S instruction to refer the dividend and divisor.
The flag is forced to be cleared by executing the DIV0U instruction.
[bit8] T: Step trace trap flag
This flag enables or disables step trace traps.
Value
0
1
This bit is initialized to "0" at a reset.
The step trace trap function is used by the emulator. When it is being used by the emulator, it cannot be
used in the user program.
36
Indicates that the operation has resulted in no overflow.
Indicates that the operation has resulted in an overflow.
Indicates that the operation has generated neither a carry nor borrow.
Indicates that the operation has generated a carry or borrow.
10
9
D1
D0
Disables step trace traps.
Enables step trace traps.
This disables all of user NMIs and user interrupts.
Description
Description
8
[Initial value]
XX0
T
B
Description
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