Fujitsu MB91260B Series Hardware Manual page 184

Figure 9.2-2 Block Diagram of 8-bit PPG (ch1, ch5, ch9, ch13)
Borrow of ch(n+1)
Machine clock divided-by-64
Machine clock divided-by-16
Machine clock divided-by-4
Machine clock
Count clock
selection
"H"/"L" select
n = 1,5,9,13
PPG
output latch
Inversion
PCNT (down counter)
Reload
"H"/"L" selector
PRLLn PRLBHn
PRLHn
CHAPTER 9 PPG (Programmable Pulse Generator)
To Port
Clear
PENn
S
R Q
PUFn
PIEn
Data bus for "L" side
Data bus for "H" side
PPGCn/TRG
Operation mode
(control)
IRQn
Borrow of
ch(n-1)
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