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■ CLK Synchronous Mode
●
Transfer Data Format
The UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.3-2 shows the
relationship between send and receive clocks and data.
Writing to SODR
SCK
RXE,TXE
SIN,SOT
When the internal clock (U-TIMER) has been selected, a data receive synchronous clock is automatically
generated as soon as data is received. While an external clock has been selected, after checking the
existence of data in the send data buffer SODR register of the send side UART (TDRE flag is "0"), an
accurate supply of the clock for one byte is necessary. Before sending starts and after it ends, be sure to set
the mark level.
The data length is 8 bits only, and no parity can be added. Only overrun errors are detected because there is
no start or stop bit.
●
Initialization
The following shows the setting values of the control registers required to use CLK synchronous mode.
(1) SMR register
MD1, MD0 : "10
CS
SCKE
(2) SCR register
PEN
P, SBL, A/D : These bits are meaningless
CL
REC
RXE, TXE
(3) SSR register
RIE
TIE
Figure 13.3-2 Transfer Data Format (Mode 2)
1
0
1
LSB
Transferred data is 01001101
"
B
: Specifies the clock input
: Set to "1" for an internal timer and to "0" for an external clock
: "0"
: "1"
: "0" (to initialize the register)
: At least one of the bits must be set to "1"
: Set to 1 to enable interrupts and to "0" to disables interrupts
: "0"
1
0
0
1
0
MSB
B
CHAPTER 13 UART
Mark
(Mode 2)
315
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