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16.3
Operation Explanation
DMAC is a multifunctional DMA controller for controling the high-speed data transfer
without using CPU instruction.
■ Overview of Operation
This block is a multi-function DMA controller able to transfer data at high speed without using CPU
instructions.
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Main operation
• The operation of each function can be set independently for each channel.
• Once enabled, a channel does not actually start transfer until the specified transfer request is detected.
• On detecting a transfer request, the DMAC outputs a DMA transfer request to the bus controller and
starts transfer on receiving bus access rights from the bus controller.
• The transfer sequence is determined by the mode which can be set independently for each channel.
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Transfer mode
Each DMA channel operates transfer in accordance with the transfer mode set by the MOD1 and MOD0
bits in its DMACB register.
Block/step transfer
Only transfers one block of data for each transfer request. Once the transfer completes, DMA removes
its transfer request from the bus controller until the next transfer request is received.
Size of transfer block: Block size specified in DMACA:BLK3 to BLK0
Burst transfer
On receiving a transfer request, transfer continues for the specified number of transfers.
Specified number of transfers: Block size × transfer count
(DMACA:BLK3 to BLK0 × DMACA:DTC15 to DTC0)
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Transfer type
Two-cycle transfer (Normal transfer)
The DMA controller treats a read and write operation as a single unit.
The DMAC reads the value from the address set in the transfer source register and then writes it to the
address in the transfer destination register.
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Transfer address
The following types of addressing are supported. This can be specified independently for each channel
transfer source and destination.
Address setting for two-cycle transfer
Accesses the addresses read from the registers in which the address values have previously been set
(DMASA and DMADA).
CHAPTER 16 DMAC (DMA Controller)
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