Fujitsu MB91260B Series Hardware Manual page 46

■ Instruction Overview
The FR family supports a set of general RISC instructions and the logical operation, bit manipulation, and
direct addressing instructions optimized for embedded controller applications as well.
instruction set is listed in APPENDIX E. Individual instructions are 16 bits long (some instructions are 32
or 48 bits long), allowing memory to be used efficiently.
The instruction set is divided into the following function groups:
• Arithmetic operation
• Load and store
• Branch
• Logical operation and bit manipulation
• Direct addressing
• Other
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Arithmetic operation
This group of instructions includes typical arithmetic operation instructions (add, subtract, compare) and
shift instructions (logical shift, arithmetic operation shift). The add and subtract instructions can also serve
for the carry producing operation used for a multiword operation and the operation with fixed flag value
useful for address calculation.
This group also includes 32×32-bit and 16×16-bit multiply instructions and a 32/32-bit step divide
instruction.
Also included are the immediate-value transfer instruction which sets an immediate value to a register and
the register-to-register transfer instruction.
All of the arithmetic operation instructions perform operations using the general-purpose and
multiplication/division registers in the CPU.
●
Load and store
The load and store instructions read from and write to external memory. These are also used to read from
and write to on-chip peripheral resources (I/O).
The load and store instructions support three different access lengths: byte, halfword, and word. They also
support general register-indirect memory addressing, and some of them support register-indirect memory
addressing with displacement and register-indirect memory addressing with register increment/decrement
as well.
●
Branch
This group of instructions serves for branching, calling, interrupting, and returning, Some of the branch
instructions have a delay slot and the others do not, allowing optimization for specific applications. The
branch instructions are detailed later in Section 3.6 "Branch Instructions".
●
Logical operation and bit manipulation
The logical operation instructions can perform a logical operation of AND, OR, or EOR either between
general-purpose registers or between a general-purpose register and memory (or an I/O). The bit manipulation
instructions can directly manipulate the content of memory (or an I/O). This group of instructions supports
general register-indirect memory addressing.
CHAPTER 3 CPU AND CONTROL UNITS
The entire
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