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■ DMAC-ch.0, ch.1, ch.2, ch.3, ch.4 Transfer Source/Transfer Destination Address
Setting Registers
[DMASA0 to DMASA4/DMADA0 to DMADA4]
These registers control the operation of each DMAC channel. A separate register is provided for each
channel.
The function of each bit is as follows.
• ch.0 to ch.3
bit
31
30
bit
15
14
(Initial value: 00000000_00000000_00000000_00000000
bit
31
30
bit
15
14
(Initial value: 00000000_00000000_00000000_00000000
• ch.4
bit
31
30
bit
15
14
(Initial value: 00000000_00000000_00000000_00000000
bit
31
30
bit
15
14
(Initial value: 00000000_00000000_00000000_00000000
These registers store the source and destination addresses for DMA transfer. The registers for ch.0 to ch.3
are 20-bit and the registers for ch4 are 24-bit.
[bit31 to bit0] DMASA (DMA Source Addr) *: Transfer source address setting
Sets the transfer source address.
[bit31 to bit0] DMADA (DMA Destination Addr) *: Transfer destination address setting
Sets the transfer destination address.
When DMA transfer starts, the contents of these registers are copied to the count buffer for the dedicated
DMA address counter and the address count is updated after each transfer in accordance with the settings.
When DMA transfer completes, the value of the counter buffer is written back to these registers and the
DMA operation ends. Accordingly, you cannot read the value of the address counter during DMA operation.
29
28
27
26
25
13
12
11
10
DMASA0 to DMASA3 [15:0]
29
28
27
26
25
13
12
11
10
DMADA0 to DMADA3 [15:0]
29
28
27
26
13
12
11
10
29
28
27
26
13
12
11
10
24
23
22
21
9
8
7
6
5
B)
24
23
22
21
9
8
7
6
5
B)
25
24
23
22
21
9
8
7
6
DMASA4[15:0]
B)
25
24
23
22
21
9
8
7
6
DMADA4[15:0]
B)
CHAPTER 16 DMAC (DMA Controller)
20
19
18
17
DMASA0 to DMASA3 [19:16]
4
3
2
1
20
19
18
17
DMADA0 to DMADA3 [19:16]
4
3
2
1
20
19
18
17
DMASA4[23:16]
5
4
3
2
1
20
19
18
17
DMADA4[23:16]
5
4
3
2
1
16
0
16
0
16
0
16
0
381
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