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■ PDIVR (Ratio of Dividing Frequency Control Register)
PDIVR0/1
Ch0:0000E9
Ch1:0000EB
This register is used in the division cycle measurement mode (PWCSR bit2, bit1, bit0: MOD2, MOD1,
MOD0=001
In the division cycle measurement mode, divide the input pulse in the count pin by the divide-by rate set in
this register and measure one cycle width after divided. Select the divide-by rate as shown below.
DIV2
0
0
0
0
1
1
1
1
• Initialized to "000
• The read / write is possible.
• These bits must not be updated after starting. These bits must be written before starting or after stopped.
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
Bit7
Bit6
-
H
H
Read/Write →
-
Initial value →
(X)
), and invalid in other modes.
B
DIV1
DIV0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
" at resetting.
B
Bit5
Bit4
-
-
-
-
-
-
(X)
(X)
(X)
1
2
=2 dividing frequency [Initial value]
Bit3
Bit2
Bit1
-
DIV2
DIV1
-
R/W
R/W
(X)
(0)
(0)
Divide Ratio Selection
2
2
=4 dividing frequency
3
2
=8 dividing frequency
4
2
=16 dividing frequency
5
2
=32 dividing frequency
6
2
=64 dividing frequency
7
2
=128 dividing frequency
8
2
=256 dividing frequency
Bit0
DIV0
R/W
(0)
191
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