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CHAPTER 16 DMAC (DMA Controller)
■ Data Type
The data length (data width) transferred in each transfer cycle can be selected from the following options.
•
byte
•
halfword
•
word
As word boundaries still apply during DMA transfer, setting a transfer source or destination address setting
that conflicts with the data length causes the lower bits to be ignored.
• word:
• halfword: Two bytes starting from an actual access addresses with the least significant bit = 0.
• byte:
If the lower bits of the transfer source and destination addresses do conflict, the specified address is
outputted on the internal address bus without modification, but the actual bus access occurs at the address
corrected in accordance with the above rules.
■ Control of Number of Transfers
The number of transfers can be set to any 16-bit value (1 to 65536 transfers). Set the number of transfers in
the transfer count register (DMACA:DTC).
The register value is copied to a temporary buffer when transfer starts and is decremented by the transfer
count counter. When the count value reaches zero indicating that the specified number of transfers has
completed, the channel either halts transfer or waits for the next trigger (if reload is enabled).
Features of the transfer count register
• Each register consists of 16 bits.
• Each register has its own reload register.
• Setting the register to "0" results in transfer being performed 65536 times.
Reload operation
• Only used for registers with a reload function and for which the reload function is enabled.
• The initial value of the count register is saved in the reload register when transfer starts.
• Once the operation of the transfer count counter causes the count to reach "0", a signal indicating
transfer completion is outputted, and then the initial value is read from the reload register and written to
the count register.
■ CPU Control
When a DMA transfer request is received, DMA issues a transfer request to the bus controller.
The bus controller assigns usage rights for the internal bus to DMA at the next appropriate timing in bus
operation, and then DMA transfer starts.
●
DMA transfer and interrupts
• During DMA transfer, interrupts are generally not received until the transfer ends.
• If a DMA transfer request occurs during interrupt processing, the transfer request is received and
interrupt processing halts until the transfer completes.
• Exceptions to this are the NMI request and interrupt requests with a level higher than the hold override
level set in the interrupt controller. In these cases, the DMAC temporarily removes its transfer request
from the bus controller at the next transfer boundary (one of block) and pauses the transfer until the
interrupt request is cleared. The transfer request is held internally during this time. Once the interrupt
request is cleared, the DMAC issues another transfer request to the bus controller to obtain bus usage
rights and restarts DMA transfer.
392
Four bytes starting from an actual access addresses with the lower 2-bit = 00
The specified address is used as the actual access address.
.
B
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