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CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
■ DSP-LY (Delayed Register)
DSP-LY is a 16-bit register. It is used when the MAC command delay write bit (LDLY) of the
multiplication and addition macro is set to "1". Access is not possible during calculation (DSP-CSR:
RunDSP = 1).
• When the MAC command LDLY bit is set to "1", the following two operations are performed.
1. The contents of the DSP-LY register are sent to the LY-DLY register.
2. The Y-RAM read data selected by means of the MAC command is stored in the DSP-LY register.
• When the MAC command's STLY bit is "1", after the MAC command executes, the value of the LY-
DLY register is written to the Y-RAM address selected by the MAC command. At this time, the
execution time is two cycles.
Bit:
DSP-LY
Address: 0003A2
H
• At reset: Indeterminate.
• Although read/write is enabled, access is only possible when DSP-LY calculation is halted (DSP-CSR:
RunDSP = 0). When a calculation is running (DSP-CSR: RunDSP =1), access from the CPU is not
possible because it is separated from the bus.
■ DSP-OT0 to DSP-OT7 (Variable Monitor Register)
There are eight 16-bit registers for use as variable monitor registers. With the exception of the initial status
when the power is turned on, the same value as addresses 0 to 7 of Y-RAM is held. Only read is always
available from the CPU. Even if calculation is ongoing, the contents of addresses 0 to 7 in Y-RAM can be
monitored.
Bit:
DSP-OT0 0003A4
H
DSP-OT1 0003A6
H
DSP-OT2 0003A8
H
DSP-OT3 0003AA
H
DSP-OT4 0003B0
H
DSP-OT5 0003B2
H
DSP-OT6 0003B4
H
DSP-OT7 0003B6
H
• At reset: Indeterminate.
• Only read can always be performed. Read is also possible if multiplication and addition macro program
execution is ongoing.
358
15
14
13
12
11
(R/W)
(R/W)
(R/W)
X
X
X
15
14
13
12
11
(R)
(R)
(R)
(R)
(R)
X
X
X
X
X
10
9
8
7
6
(R/W)
(R/W)
X
X
10
9
8
7
6
(R)
(R)
(R)
(R)
(R)
X
X
X
X
X
5
4
3
2
1
(R/W)
(R/W)
(R/W)
X
X
X
5
4
3
2
1
(R)
(R)
(R)
(R)
(R)
(R)
X
X
X
X
X
0
Write
Read
Read/Write
Initial value
0
Read only
Read/Write
X
Initial value
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