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CHAPTER 3 CPU AND CONTROL UNITS
●
PC (Program Counter)
PC
[bit31 to bit0]
The program counter contains the address of the instruction currently being executed.
When the PC is updated as an instruction is executed, bit0 is set to "0". Bit0 may be set to "1" only when
an odd-numbered address is specified as the branch destination address. Even in that case, however, bit0 is
invalid and the instruction must be placed at an address that is a multiple of the number 2.
The initial value after a reset is indeterminate.
●
TBR (Table Base Register)
TBR
The table base register contains the start address of the vector table used for servicing EIT events.
The initial value after a reset is 000FFC00
●
RP (Return Pointer)
RP
The return pointer contains the return address of a subroutine.
When the CALL instruction is executed, the value in the PC is transferred to the RP.
When the RETI instruction is executed, the value in the RP is transferred to the PC.
The initial value after a reset is indeterminate.
●
SSP (System Stack Pointer)
SSP
The SSP is a system stack pointer.
It serves as R15 of the general-purpose register when the S-flag contains "0".
The SSP can be explicitly specified. The SSP is also used as the stack pointer that specifies the stack for
saving the PS and PC when an EIT event occurs.
The initial value after a reset is "00000000
38
31
31
H
31
31
H
0
[Initial value]
XXXXXXXX
0
[Initial value]
000FFC00
.
0
[Initial value]
XXXXXXXX
0
[Initial value]
00000000
".
H
H
H
H
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