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CHAPTER 3 CPU AND CONTROL UNITS
■ CPU
The CPU is a compact implementation of a 32-bit RISC based FR architecture.
The CPU employs a five-stage instruction pipeline to execute one instruction in one cycle.
The pipeline consists of the following stages:
•
Instruction fetch (IF) ......... Outputs the instruction address to fetch the instruction.
•
Instruction decode (ID) .... Decodes the fetched instruction.
•
Execution (EX) ................. Executes the operation.
•
Memory access (MA)........ Access memory for loading or storing.
•
Write back (WB) .............. Writes the operation result (or loaded memory data) to the register.
CLK
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instructions are not executed out of order. That is, if instruction A enters the pipeline ahead of instruction
B, instruction A always reaches the writeback stage before instruction B.
In principle, instructions are executed at a rate of one instruction per cycle. Note, however, that a load/
store instruction involving a memory wait state, a branch instruction with no delay slot, or a multi-cycle
instruction requires more than one cycle for execution. Also, a delay in supplying an instruction slows
down the execution speed of the instruction.
■ 32-bit↔16-bit Bus Converter
This bus converter provides the interface between the 32-bit F-bus for fast access and the 16-bit R-bus,
enabling data access from the CPU to built-in peripheral resources.
When the CPU attempts to make a 32-bit access, this bus converter converts it to two 16-bit accesses to the
R-bus. Some of the built-in peripheral circuits have an access width restriction.
■ Harvard↔Princeton Bus Converter
This bus converter delivers consistency between CPU instruction access and data access to provide a
smooth interface to the external bus.
The CPU has the Harvard architecture in which the instruction and data buses are independent of each
other. In contrast, the bus controller for controlling the external bus has the Princeton architecture with a
single bus. This bus converter assigns priorities to CPU instruction and data accesses to control access to
the bus controller. This always optimizes the order of accesses to the external bus.
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Also, reads a register.
Figure 3.2-2 Instruction Pipeline
WB
MA
WB
EX
MA
ID
EX
IF
ID
IF
WB
MA
WB
EX
MA
ID
EX
WB
MA
WB
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