Fujitsu MB91260B Series Hardware Manual page 93

CHAPTER 3 CPU AND CONTROL UNITS
[bit11] SRST (Software ReSeT occurred)
This bit indicates whether a reset (RST) by writing to the SRST bit (software reset) in the STCR register
has occurred.
0
1
• The bit is initialized to "0" immediately after either a reset (INIT) by INIT pin input or a read.
• A read is possible; a write does not affect the bit value.
[bit10] (reserved bit)
[bit9, bit8] WT1,WT0 (Watchdog interval Time select)
These bits are used to specify the time interval required for the watchdog timer.
The combination of values written to these bits selects the time interval for the watchdog timer from among
the four options listed below.
WT1
0
0
1
1
(φ represents the internal base clock period.)
• These bits are initialized to "00
• A read is possible; a write is valid only once after a reset (RST). Any further write is invalid.
■ STCR: Standby Control Register
Address: 000481
Initial value (INIT pin)
Initial value (INIT)
Initial value (RST)
This register controls the operation mode of the device.
The register controls the transition to each of the two standby modes (stop and sleep modes), controls the
pin status and oscillation disable mode during the stop mode, sets the oscillation stabilization wait time, and
issues a software reset.
78
RST by software reset has not occurred.
RST by software reset has occurred.
Minimum write-to-CTBR interval
WT0 required for suppressing watchdog
φ × 2 16
0
φ × 2 18
1
φ × 2 20
0
φ × 2 22
1
" at a reset (RST)
B
Bit 7
STOP SLEEP
H
R/W
0
0
0
reset
(Initial value)
6 5 4
HIZ SRST
R/W R/W R/W
0 1 1
0 1 1
0 × 1
Time from last 5AH write to CTBR until
watchdog reset
φ × 2 16 to φ × 2
φ × 2 18 to φ × 2
φ × 2 20 to φ × 2
φ × 2 22 to φ × 2
3 2 1
OS1 OS0 – OSCD1
R/W R/W R/W
0 0 1
× × 1
× × ×
17
19
21
23
0
R/W
1
1
×