Fujitsu MB91260B Series Hardware Manual page 141

CHAPTER 5 INTERRUPT CONTROLLER
●
Hardware configuration
The flow of each signal is illustrated below.
This module
IRQ
I-UNIT
(ICR)
(HRCL)
●
Sequence
RUN
CPU
Bus access
request
DHREQ
DHACK
IRQ
LEVEL
MHALTI
If an interrupt request is generated and the interrupt level becomes higher than that set in the HRCL
register, MHALTI becomes active to the DMA controller. Then the DMA controller cancels the access
request, allowing the CPU to return from the hold status for servicing the interrupt.
Given below is an example of handling multiple interrupts.
Figure 5.3-3 Interrupt Level: HRCL < ICR (Interrupt I) < ICR (Interrupt II)
RUN
CPU
Bus access
request
DHREQ
DHACK
IRQ1
IRQ2
LEVEL
MHALTI
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Figure 5.3-1 Flow of Each Signal
Bus access request
MHALTI
DMAC
Converter
Figure 5.3-2 Interrupt Level: HRCL < ICR (LEVEL)
Bus hold
Bus hold
Interrupt I
DHREQ
CPU
Bus
DHACK
Interrupt service
1) 2)
Interrupt service II
3) 4) 1)
DHREQ: D-bus hold request
DHACK: D-bus hold acknowledge
IRQ: Interrupt request
MHALTI: Hold request cancel request
Bus hold (DMA transfer)
Example of interrupt
routine
1) Interrupt request clear
2) RETI
Bus hold (DMA transfer)
Interrupt service I
2)
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