Fujitsu MB91260B Series Hardware Manual page 100

The combination of values written to the bits selects one of the following three types of clock source as
shown below.
CLKS1
0
0
1
1
• These bits are initialized to "00
• A read and a write are possible.
Notes:
• The value of the CLKS0 bit (bit8) cannot be changed with the CLKS1 bit (bit9) containing "1".
• The bits must not be set to any other combination of values.
■ DIVR0: Base Clock Divide Ratio Setting Register 0
This register controls the frequency divide ratio for each type of internal clock signal relative to the base
clock signal.
The register sets the divide ratios for the CPU/internal bus clock signal (CLKB) and for the peripheral
circuit/peripheral bus clock signal (CLKP).
If you set a combination of the source clock, main PLL multiplier, and divide ratio, which results in a
frequency higher than the maximum operating frequency, the operation of the device is not guaranteed.
Use meticulous care not to set such a combination of values. Also be careful not to select the source clock
and change settings in wrong order.
When the divide ratio setting in this register is changed, the new setting takes effect at the next clock rate.
[bit15 to bit12] B3, B2, B1, B0 (clkB divide select 3 to 0)
These bits are used to set the CPU clock (CLKB) frequency divide ratio.
The clock frequency divide ratio set by these bits applies to the clock signal (CLKB) for the CPU, internal
CLKS0
0 Frequency-halved version of oscillation input from X0/X1 (Initial value)
1 Setting disabled
0 Main PLL
1 Setting disabled
B
[Combination that can be changed]
bit 15
Address: 000486
B3
H
R/W
Initial value (INIT)
Initial value (RST)
CHAPTER 3 CPU AND CONTROL UNITS
Clock source setting
" at a reset (INIT).
" → "10
"00 "
B B
" → "00
"10 "
B B
14 13 12
B2 B1 B0
R/W R/W R/W
0 0 0
× × ×
11 10
P3 P2 P1
R/W R/W R/W
0 0 0
× × ×
9 8
P0
R/W
1 1
× ×
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