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[Stop-state return sources]
•
Occurrence of a specific (clock-free) valid interrupt request
Only some external interrupt and NMI input pins are valid.
When a request for an interrupt not disabled (1111
canceled and the device enters the oscillation stabilization wait RUN state. In this case, set the I-flag in
the PS register of the CPU to "1" to enable interrupts and execute the interrupt handler after returning
from the stop state.
The stop mode is not canceled even when a request for an interrupt disabled (1111
occurs.
•
Occurrence of a setting initialization reset (INIT) request
When a setting initialization reset (INIT) request occurs, the device enters the setting initialization reset
(INIT) state unconditionally.
•
Occurrence of an operation initialization reset (RST) request
When an operation initialization reset (RST) request occurs, the device enters the operation
initialization reset (RST) state unconditionally.
For the priority of each type of source, see "● Priorities of state transition requests" of the section 3.12
"Device Status Control".
[Selecting the clock source for the stop mode]
In self-oscillation mode, select the frequency-halved version of the main clock signal as the source clock
signal before setting the stop mode. For details, see Section "3.11.1 PLL Control" therein.
Note that the restrictions on the divide ratio setting are the same as those for normal operation.
[Synchronous standby operation]
When the SYNCS bit (bit8) in the TBCR (timebase counter control register) contains "1", the synchronous
standby operation is enabled. In this case, the device does not enter the stop state only by writing to the
STOP bit. It enters the stop state by reading the STCR register after that.
To enter the stop mode, be sure to use the sequence given in [Transition to stop mode].
CHAPTER 3 CPU AND CONTROL UNITS
) in the ICR register occurs, the stop mode is
B
) in the ICR register
B
99
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