Fujitsu MB91260B Series Hardware Manual page 302

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This non-overlapping signal is generated via normal-polarity PPG (16-bit dead timer control register
(DTCR0, DTCR1, and DTCR2) TMD 8 to TMD0 (higher-order bits are 10 to 8; lower-order bits are 2 to
0) = 111 ).
B
When the DTCR0, DTCR1, and DTCR2 register's DMOD2 to DMOD0 (higher-order bit is 15; lower-order
bit is 7) selects the non-overlapping signal with a value of 0 (normal polarity), a delay equivalent to the
non-overlap time set in the 16-bit dead timer register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) is
applied. This delay is applied to the PPG0 timer pulse signal or reverse signal's rising edge. If the PPG0
timer pulse width is less than the specified non-overlap time, the 16-bit dead timer starts counting down
again from the TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 value of the edge following that PPG0
pulse.
Figure 11.6-26 Non-overlap Signal Generated by PPG0 Timer of Normal Polarity
<Register setting>
TCDTH, TCDTL
TCCSH, TCCSL
CPCLRH, CPCLRL
OCCPH0 to OCCPH5, OCCPL0 to OCCPL5 : XXXX
OCSH0 to OCSH5, OCSL0 to OCSL5
DTCR0 to DTCR2
TMRRH0 to TMRRH2, TMRRL0 to TMRRL2 : XXXX
SIGCR1 : XXXXXXXX (Setting of DTTI input and 16-bit dead timer count clock)
B
Note: Be sure to set according to "X" operation.
16-bit dead timer 0
Count value
TMRR0 set
value
PPG0
RTO0(U)
RTO1(X)
: XXXX
H
: XXXXXXXX X0X0XXXX
: XXXX (Setting of cycle)
H
(Compare value)
H
: -XX1XXXX XXXXXX11
: 0XXXX111
B
(Setting of non-overlap timing)
H
2 machine cycle
Pin name
RTO0 (U) Delayed signal is applied at rising edge of PPG0.
RTO2 (V) Delayed signal is applied at rising edge of PPG0.
RTO4 (W) Delayed signal is applied at rising edge of PPG0.
RTO1 (X) Delayed inverted signal is applied at falling edge of PPG0.
RTO3 (Y) Delayed inverted signal is applied at falling edge of PPG0.
RTO5 (Z) Delayed inverted signal is applied at falling edge of PPG0.
CHAPTER 11 MULTIFUNCTIONAL TIMER
PCSR : XXXX
H
PDUT : XXXX
B H
PCNT : XXXX
H
B
Output signal
Time
2 machine cycle
287