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Appendix Table E-15 20-Bit Delayed Branch Macro Instruction
Mnemonic
*CALL20:D label20,Ri
*BRA20:D label20,Ri
*BEQ20:D label20,Ri
*BNE20:D label20,Ri
*BC20:D label20,Ri
*BNC20:D label20,Ri
*BN20:D label20,Ri
*BP20:D label20,Ri
*BV20:D label20,Ri
*BNV20:D label20,Ri
*BLT20:D label20,Ri
*BGE20:D label20,Ri
*BLE20:D label20,Ri
*BGT20:D label20,Ri
*BLS20:D label20,Ri
*BHI20:D label20,Ri
[Reference 1] CALL20:D
(1) If label20-PC-2 is between -0x800 and +0x7fe, the following instruction will be generated:
CALL:D label12
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:20 #label20,Ri
CALL:D @Ri
[Reference 2] BRA20:D
(1) If label20-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
BRA:D label9
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
LDI:20 #label20,Ri
JMP:D @Ri
[Reference 3] Bcc20:D
(1) If label20-PC-2 is between -0x100 and +0xfe, the following instruction will be generated:
Bcc:D label9
(2) If label20-PC-2 is outside the range of (1) or contains an external reference symbol, the following instruction will be
generated:
Bxcc false
xcc is the opposite condition of cc.
LDI:20 #label20,Ri
JMP:D @Ri
false:
Operation
Address of the next instruction +2->RP,
label20->PC
label20->PC
if(Z==1) then label20->PC
↑ s/Z==0
↑ s/C==1
↑ s/C==0
↑ s/N==1
↑ s/N==0
↑ s/V==1
↑ s/V==0
↑ s/V xor N==1
↑ s/V xor N==0
↑ s/(V xor N) or Z==1
↑ s/(V xor N) or Z==0
↑ s/C or Z==1
↑ s/C or Z==0
APPENDIX E Instruction Lists
Remarks
RRi: Temporary register (See Reference 1)
Ri: Temporary register (See Reference 2)
Ri: Temporary register (See Reference 3)
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471
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