Fujitsu MB91260B Series Hardware Manual page 65

CHAPTER 3 CPU AND CONTROL UNITS
■ I-flag
This flag enables or disables interrupts. It is provided as CCR bit 4 in the PS register.
Value
0
1
■ ILM Register
The interrupt level mask (ILM) register is the PS register (bit20 to bit16) that holds an interrupt level mask
value.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level indicated
in the ILM register.
The highest level value is 0 (00000
The level value which can be set in the program is limited. When the original value is 16 to 31, the new
value which can be set is 16 to 31. After an instruction which sets a value of 0 to 15 is executed, a value of
(the specified value + 16) is transferred.
When the original value is 0 to 15, any value from 0 to 31 can be set. The STILM instruction is used to set
this register.
■ Interrupt/NMI Level Masking
If an NMI or interrupt request occurs, the interrupt level of the interrupt source (see Table 3.8-1) is
compared with the level mask value held in the ILM register. The request is masked and rejected when the
following condition is satisfied:
Interrupt level of the source ≥ Level mask value
50
Disables interrupts.
The flag is cleared to "0" when the INT instruction is executed.
(Note that the value saved to the stack is the one existing before the flag is cleared.)
Enables interrupts.
The masking of interrupt requests is controlled by the level value held in the ILM register.
); the lowest is 31 (11111
B
Description
).
B