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CHAPTER 3 CPU AND CONTROL UNITS
[bit13 to bit11] TBC2 to TBC0 (TimeBasetimer Counting time select)
These bits are used to set the time interval required for the timebase counter used for the timebase timer.
The combination of values written to these bits selects the time interval for the timebase counter from
among the eight options listed below.
TBC2
0
0
0
0
1
1
1
1
(φ represents the internal base clock period, or the main PLL output period.)
• The initial value is indeterminate. Be sure to set a value before enabling interrupts.
• A read and a write are possible.
[bit10] (reserved bit)
This bit is a reserved bit. The value read is indeterminate. A write to this bit has no effect on any function
of the register.
[bit9] SYNCR (SYNChronous Reset enable)
This bit serves as the synchronous reset operation enable bit.
The bit selects one of the two types of reset operation to be performed when an operation initialization reset
(RST) request or hardware standby request has occurred. One is the normal reset operation for prompt
transition to the reset (RST) or hardware standby state as soon as the request is issued. The other is the
synchronous reset operation for transition to the operation initialization reset (RST) or hardware standby
state after all bus accesses terminate.
0
1
• The bit is initialized to "0" at a reset (INIT).
• A read and a write are possible.
82
TBC1
TBC0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Normal reset operation (Initial value)
Synchronous reset operation
Timer interval
φ × 2
11
φ × 2
12
φ × 2
13
φ × 2
22
φ × 2
23
φ × 2
24
φ × 2
25
φ × 2
26
Oscillation frequency of 4 MHz
and PLL multiplier of 8x
64 µs
128 µs
256 µs
131 ms
262 ms
524 ms
1048 ms
2097 ms
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