Table of Contents
Advertisement
[bit5] S: Stack flag
This flag specifies the stack pointer to be used as R15.
Value
Selects the SSP to be used as R15.
The bit is set to "0" automatically when an EIT occurs.
0
(Note, however, that the value saved to the stack is the one existing before the bit is
cleared.)
1
Selects the USP to be used as R15.
This bit is cleared to "0" at a reset.
Set the bit to "0" for execution of the RETI instruction.
[bit4] I: Interrupt enable flag
This flag controls the enabling or disabling of user interrupt requests.
Value
Disables user interrupts.
The bit is cleared to "0" upon execution of the INT instruction.
0
(Note, however, that the value saved to the stack is the one existing before the bit is
cleared.)
Enables user interrupts.
1
The masking of user interrupt requests is controlled by the value held in the ILM register.
This bit is cleared to "0" at a reset.
[bit3] N: Negative flag
This flag indicates the sign to be used for the operation result regarded as an integer represented in two's
complement.
Value
0
Indicates the operation result as a positive value.
1
Indicates the operation result as a negative value.
The initial state after a reset is indeterminate.
[bit2] N: Zero flag
This flag indicates whether the operation result is "0".
Value
0
Indicates that the operation result is a value other than "0".
1
Indicates that the operation result is "0".
The initial state after a reset is indeterminate.
CHAPTER 3 CPU AND CONTROL UNITS
Description
Description
Description
Description
35
Advertisement
Table of Contents
