Fujitsu MB91260B Series Hardware Manual page 329

CHAPTER 13 UART
■ Asynchronous (Start-stop Synchronization) Mode
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Transfer Data Format
UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.3-1 shows the data format.
SIN, SOT
As shown in Figure 13.3-1, the transfer data always starts with the start bit ("L" level data), continues to the
data bit length specified in LSB First, and ends with a stop bit ("H" level data). If an external clock is
selected, be sure to input a clock at all times.
The data length can be set to 7 or 8 bits in normal mode (Mode 0), but must be set to 8 bits in
multiprocessor mode (Mode 1). In multiprocessor mode, parity cannot be added. Instead, the A/D bit is
always added.
●
Receive Operation
If the RXE bit (bit1) of the SCR register is set to "1", a receive operation is always in progress.
If a start bit appears on the receive line, one-frame data is received according to the data format specified in
the SCR register. After reception of one frame is completed, if an error occurs, the error flag is set and then
the RDRF flag (bit4 of the SSR register) is set. If, at this time, the RIE bit (bit1) of the same SSR register
is set to "1", a receive interrupt is generated to the CPU. Check the flags of the SSR register and if normal
reception has occurred, read the SIDR register, or if an error has occurred, perform the necessary
processing.
The RDRF flag is cleared when the SIDR register is read.
●
Send Operation
If the TDRE flag (bit3) of the SSR register is set to "1", send data is written to the SODR register. If, at
this time, the TXE bit (bit0) of the SCR register is set to "1", transmission occurs.
The TDRE flag is set again when the data set in the SODR register is loaded into the send shift register and
the transfer starts, indicating that the next send data can be set. If, at this time, the TIE bit (bit0) of the same
SSR register is set to "1", a send interrupt is generated to the CPU to request to set send data in the SODR
register.
The TDRE flag is cleared if data is set in the SODR register.
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Figure 13.3-1 Transfer Data Format (Modes 0 and 1)
0 1 0 1 1
Start LSB
Transferred data is 01001101
0 0 1 0 1
MSB Stop
A/D Stop
.
B
1
(Mode 0)
(Mode 1)