Multifunctional Timer Register - Fujitsu MB91260B Series Hardware Manual

11.4

Multifunctional Timer Register

This section describes the multifunctional timer registers.
■ 16-bit Free-run Timer Register
Compare clear buffer register, Compare clear register (Upper)
CPCLRBH/CPCLRH
Address: 0000A4
CPCLRBH Write →
CPCLRH Read →
Initial value →
Compare clear buffer register, Compare clear register (Lower)
CPCLRBL/CPCLRL
CPCLRBL Write →
CPCLRL Read →
Initial value →
Timer data register (Upper)
TCDTH
Address: 0000A6
Timer data register (Lower)
TCDTL
Timer state control register (Upper)
TCCSH
Address: 0000A8
Timer state control register (Lower)
TCCSL
Address: 0000A9
A/D trigger control register
ADTRGC
Address: 0000AB
Bit15 Bit14
CL15 CL14
H
W W
R R
(1) (1)
Bit7 Bit6
CL07 CL06
W W
R R
(1) (1)
Bit15 Bit14
H
T15 T14
Read/Write →
R/W R/W
Initial value →
(0) (0)
Bit7 Bit6
T07 T06
Read/Write →
R/W R/W
Initial value →
(0) (0)
Bit15 Bit14
H ECKE IRQZF
Read/Write →
R/W R/W
Initial value →
(0) (0)
Bit7 Bit6
H
BFE STOP
Read/Write →
R/W R/W
Initial value →
(0) (1)
Bit7 Bit6
H
- -
Read/Write →
- -
Initial value →
(X) (X)
CHAPTER 11 MULTIFUNCTIONAL TIMER
Bit13 Bit12 Bit11
CL13 CL12 CL11
W W W
R R R
(1) (1) (1)
Bit5 Bit4 Bit3
CL05 CL04 CL03
W W W
R R R
(1) (1) (1)
Bit13 Bit12 Bit11
T13 T12 T11
R/W R/W R/W
(0) (0) (0)
Bit5 Bit4 Bit3
T05 T04 T03
R/W R/W R/W
(0) (0) (0)
Bit13 Bit12 Bit11
IRQZE MSI2 MSI1
R/W R/W R/W
(0) (0) (0)
Bit5 Bit4 Bit3
MODE SCLR CLK3 CLK2
R/W R/W R/W
(0) (0) (0)
Bit5 Bit4 Bit3
- - SEL2
R/W
- -
(X) (X) (0)
Bit10 Bit9 Bit8
CL10 CL09 CL08
W W W
R R R
(1) (1) (1)
Bit2 Bit1 Bit0
CL02 CL01 CL00
W W W
R R R
(1) (1) (1)
Bit10 Bit9 Bit8
T10 T09 T08
R/W R/W R/W
(0) (0) (0)
Bit2 Bit1 Bit0
T02 T01 T00
R/W R/W R/W
(0) (0) (0)
Bit10 Bit9 Bit8
MSI0 ICLR ICRE
R/W R/W R/W
(0) (0) (0)
Bit2 Bit1 Bit0
CLK1 CLK0
R/W R/W R/W
(0) (0) (0)
Bit2 Bit1 Bit0
SEL1 AD2E AD1E
R/W R/W R/W
(0) (0) (0)
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