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[Single-Chip Mode]
Appendix Table C-1 Pin Status In Each CPU State (1 / 2)
Pin No.
Pin name
QFP LQFP
1
99
P23
2
100
P24
3
1
P25
4, 5
2, 3
P26, P27
6 to 9 4 to 7
P50 to 53
10
8
P54
11
9
P55
12
10
P56
13
11
P57
14
12
PG0
15
13
PG1
16
14
PG2
20
18
PG3
21
19
PG4
22
20
PG5
23 to
21 to
P40 to P47
30
28
31, 32 29, 30
PE1, PE0
38, 39 36, 37
PD1, PD0
41 to
39 to
PC7 to PC0 AN7 to AN0
48
46
51 to
49 to
P30 to P35
56
54
57, 58 55, 56
P36, P37
59, 60 57, 58
P60, P61
61, 62 59, 60
P62, P63
63, 64 61, 62
P70, P71
65
63
P72
66
64
P73
69
67
P74
70
68
P75
71
69
P76
72
70
P77
At initialize
Function
*1
INIT=L
SIN1
SOT1
SCK1
INT6-INT7
Port
INT0
INT1
INT2
INT3
CKI/INT4
PPG0/INT5
Port
SIN2
SOT2
Output
SCK2
Hi-Z/
Input
Port
disabled
AN11, AN10
AN9, AN8
RTO0 to
RTO5
IC0, IC1
IC2, IC3
INT8, INT9
TOT1, TOT2
DTTI
PWI0
PWI1
ADTG0
ADTG1
ADTG2
APPENDIX C Pin Status In Each CPU State
At sleep
*2
INIT=H
Retention of
the status
immediately
before
Input enabled
Retention of
the status
immediately
before
Input enabled
Output
Hi-Z/
Input
disabled
Retention of
the status
immediately
before
Input enabled
Retention of
the status
immediately
before
At stop
HIZ=0
HIZ=1
Retention of
the status
Output Hi-Z/
immediately
Input 0 fix
before
Input enabled
Input enabled
Retention of
Output Hi-Z/
the status
Input 0 fix
immediately
before
Input enabled
Input enabled
Retention of
the status
Output Hi-Z/
immediately
Input 0 fix
before
Input enabled
Input enabled
Retention of
the status
Output Hi-Z/
immediately
Input 0 fix
before
451
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