Fig. 2.14 Operation Of Noise Clearing Circuit - Fujitsu F2MC-8L Family series Hardware Manual

Peripherals
PWC input
Sampling clock pulse
Integrated value
Internal signal
HARDWARE CONFIGURATION
(c) Noise-clearing circuit operation
Figure 2.15 shows the operation of the noise-clearing circuit. The PWC
input is sampled by the clock pulse selected by the clock pulse select bits
(NCS1 and NCS0) of the noise-clear control register. Integrating the
sampled signal clears the noise. The maximum width of cleared noise is
as follows:
Nw = Sampling clock cycle × 5
When noise clearing is prohibited, the PWC input is input directly to the
pulse-width count timer.

Fig. 2.14 Operation of Noise Clearing Circuit

(5) Usage precautions
(a) Do not rewrite the value of PCR2 when the EN bit is 1 (during timer
operation and pulse-width measurement).
(b) At mode switching (FC bit rewriting), the state of each flag does not
change. Clear each flag immediately after the mode is switched.
(c) Read the measured value before the next underflow. When the value
is read after an underflow, the TO bit is inverted, sometimes disabling
calculation of the correct measured value.
(d) When the previous measured value is not read after continuous pulse-
width measurement, it is held without transferring the new value to the
buffer.
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