Interrupt Event Register (I_Event) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Table 11-7. ECNTRL Field Descriptions (Continued)
Bits Name
1 ETHER_EN Ethernet enable. When this bit is set, the FEC is enabled, and reception and transmission is
possible. When this bit is cleared, reception is immediately stopped and transmission is
stopped after a bad CRC is appended to any frame currently being transmitted. The buffer
descriptor(s) for an aborted transmit frame are not updated following deassertion of
ETHER_EN. When ETHER_EN is deasserted, the DMA, buffer descriptor, and FIFO control
logic are reset, including FIFO pointers.
0 RESET Ethernet controller reset. When this bit is set, the equivalent of a hardware reset is
performed but it is local to the FEC. ETHER_EN is cleared and all other FEC registers take
their reset values. Also, any transmission/reception currently in progress is abruptly aborted.
This bit is automatically cleared by hardware once the reset sequence is complete
(approximately 16 clock cycles after being set).

11.5.2 Interrupt Event Register (I_EVENT)

An event that sets a bit in I_EVENT generates an interrupt if the corresponding bit in the
interrupt mask register (I_MASK) is set. Bits in the interrupt event register are cleared
when a one is written to them. Writing a zero has no effect.
31 30
Field HBERR BABR BABT GRA
Reset
R/W
15
Field
Reset
R/W
Addr
Bits Name
31 HBERR Heartbeat error. A heartbeat was not detected within the heartbeat window following a
transmission.
30 BABR Babbling receive error. A frame was received with length in excess of MAX_FL bytes.
29 BABT Babbling transmit error. The transmitted frame length has exceeded MAX_FL bytes. This
condition is usually caused by a frame that is too long being placed into the transmit data
buffer(s). Truncation does not occur.
28 GRA Graceful stop complete. A graceful stop, which was initiated by setting X_CTRL[GTS], is now
complete. This bit is set as soon as the transmitter has finished transmitting any frame that
was in progress when GTS was set.
27 TXF Transmit frame interrupt. A frame has been transmitted and that the last corresponding buffer
descriptor has been updated.
26 TXB Transmit buffer interrupt. A transmit buffer descriptor has been updated.
29 28 27 26
TXF TXB
0000_0000_0000_0000
0000_0000_0000_0000
Table 11-8. I_EVENT Field Descriptions
Chapter 11. Ethernet Module
Description
25 24 23 22
RXF RXB MII EBERR UMINT
Read/write
—
Read/write
MBAR + 0x844
Description
Programming Model
21 20 16
—
0
11-13