Motorola DigitalDNA ColdFire MCF5272 User Manual page 428

Signal List
Table 19-2. Signal Name and Description by Pin Number (Continued)
Map
BGA
0 (Reset)
Pin
K14 D6
L1 PA11
L2 PA12
L3 PA13
L4 FSC1/FSR1/
DFSC1
L5 QSPI_CLK/
BUSW1
L6 TIN0
L7 E_Tx CLK
L8 PB10
L9 PB14
L10 E_CRS
L11 CS5
L12 D0
L13 D1
L14 D2
M1 DCL1/
GDCL1_OUT
M2 PA14
M3 PA15_INT6 DGNT1_INT6
M4 INT1/
USB_WOR
M5 QSPI_CS0/
BUSW0
M6 PB7
19-14
Pin Functions
1 2
PC6 –
– QSPI_CS1
DFSC2 –
DFSC3 –
– –
– –
– –
– –
E_TxD1 –
E_RxER –
– –
– –
PC0 –
PC1 –
PC2 –
– –
DREQ1 –
–
– –
– –
TOUT0 –
MCF5272 User's Manual
Name
3
– D6/PC6
– PA11/QSPI_CS1
– PA12/DFSC2
– PA13/DFSC3
– FSC1/FSR1/DFSC1
– QSPI_CLK / BUSW1
– TIN0
– E_Tx CLK
– PB10/E_TxD1
– PB14/E_RxER
– E_CRS
– CS5
– D0/PC0
– D1/PC1
– D2/PC2
– DCL1/GDCL1_OUT
– PA14/DREQ1
– PA15_INT6/DGNT1_INT6 Port A bit 15/PLIC port 1
– INT1/ USB_WOR
– QSPI_CS0 / BUSW0
– PB7/TOUT0
Description
D6/port C bit 6
Port A bit 11/QSPI chip
select 1
Port A bit 12/Delayed
frame sync 2
Port A bit 13/Delayed
frame sync 3
PLIC port 1 IDL
FSR/GCI
FSC1/Generated frame
sync 1 Out
QSPI serial clock/CS0
bus width bit 1
Timer 0 input
Ethernet Tx clock
Port B bit 10/Tx data bit
1 (100 Base-T Ethernet
only)
Port B bit 14/Receive
Error (100 Base-T
Ethernet only)
Carrier sense (100
base-T Ethernet only)
Chip select 5
D0/port C bit 0
D1/port C bit 1
D2/port C bit 2
PLIC ports 1, 2, 3 data
clock/Generated DCL
out
Port A bit 14/PLIC port 1
IDL D-channel request
D-channel
grant/Interrupt 6 input
Interrupt input 1/USB
wake-on-ring
QSPI peripheral chip
select 0/CS0 bus width
bit 0
Port B bit 7/Timer 0
output compare
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I/O