Motorola DigitalDNA ColdFire MCF5272 User Manual page 205

If the delay between shifted SDCLK and following internal system clock edge is shorter
than the read access time of the SDRAM, data is sampled with the true CAS latency.
Internal
CLK
SDCLK
Data
Figure 9-7. Timing Refinement with True CAS Latency and Inverted SDCLK
Selecting a system clock frequency low enough that the SDCLK-to-CLK delay is long
compared to the SDRAM read access time reduces effective CAS latency by 1 cycle.
Internal CLK
SDCLK
Data
Figure 9-8. Timing Refinement with Effective CAS Latency
When reduced effective CAS latency is used, the SDRAM is
still programmed with true CAS latency. The SDRAM
controller state machine must be reprogrammed for the
reduced CAS latency. SDRAM initialization software
CASL = 2
T
SDCLK_to_CLK
CASL = 1
Shifted delay of SDCLK
T - T > 0 => effective CAS latency reduced by 1
SDCLK_to_CLK acc
NOTE:
Chapter 9. SDRAM Controller
Solving Timing Issues with SDCR[INV]
SDRAM read access time
Delay SDCLK to CLK
Shifted delay of SDCLK
- T < 0 => true CAS latency
acc
Delay SDCLK to CLK
SDRAM read access time
9-15