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PLIC Registers
Field
Reset
R/W
Addr
Figure 13-20. Loopback Control Register (PLCR)
Bits
7-6
5-4
3-2
1-0
In loopback mode, the respective port must be enabled (using
PLCR[ON/OFF]) along with the B1 and B2 channels (using
PLCR[ENB1,
PDRQR[DCNTI] when in IDL mode, for instance). Also, if
more than one of ports 1, 2, or 3 are programmed in loopback
mode, it is necessary to program the appropriate frame sync
function using the sync delay registers discussed in
Section 13.5.21, "Sync Delay Registers (P0SDR–P3SDR)."
13.5.9 Interrupt Configuration Registers (P0ICR–P3ICR)
All bits in these registers are read/write and are cleared on hardware or software reset.
15
14
PLCIR0–3 IE
—
Reset
R/W
Addr
MBAR + 0x0358 (PLCIR0); 0x035A (PLCIR1); 0x035C (PLCIR2); 0x035E (PLCIR3)
Figure 13-21. Interrupt Configuration Registers (P0ICR–P3ICR)
The PLICR registers contain interrupt configuration bits for each of the four ports on the
MCF5272.
13-22
7
6
5
LM3
LM2
Table 13-3. PLCR Field Description
Name
LM3
Loopback mode control, port 3.
00 Normal
01 Auto-echo
10 Local Loopback
11 Remote Loopback
LM2
Loopback mode control, port 2. See LM3.
LM1
Loopback mode control, port 1. See LM3.
LM0
Loopback mode control, port 0. See LM3.
ENB2])
12
11
10
9
GCR GCT GMR GMT
0000_0000_0000_0000
MCF5272 User's Manual
4
3
2
LM1
0000_0000
Read/Write
MBAR + 0x38F
Description
NOTE:
and
the
D
channel
8
7
6
5
—
DTIE B2TIE B1TIE DRIE B2RIE B1RIE
Read/Write
1
0
LM0
(using
4
3
2
1
0
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