Table of Contents
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A
Access control register, 4-15
ACR0 and ACR1, 4-15
Activate low-power register, 6-10
Address bus, 20-2
Address variant, 5-5
Addressing
mode summary, 2-22
Addressing mode summary, 2-22
Arbitration, bus, 20-24
Architecture overview, 1-4
Async inputs signal timing, 23-17
Audience, xxxix
B
Baud rate
calculating, 16-21
selection, 14-6
Branch instruction execution
timing, 2-35
Buffer descriptors
Ethernet, 11-33
USB controller, 11-33
Buffering and impedance matching, B-1
Bus
arbitration, 20-24
burst data transfers, 20-20
configurations overview, 1-7
data transfer mechanism, 20-5
errors, 20-22
exceptions, 20-4
external interface, 1-5
external interface types, 20-10
interface for FLASH/SRAM, 20-10
interrupt acknowledge cycles, 20-21
master reset, 20-25
misaligned operands, 20-20
normal reset, 20-26
read/write (R/W), 20-2
reset operation, 20-24
sizing, 20-6
soft reset operation, 20-28
software watchdog timer reset operation, 20-27
transfer acknowledge (TA), 20-3
transfer error acknowledge (TEA), 20-4
Byte strobes, 20-10
INDEX
C
Cache
configuration register, 2-19
registers, access control, 2-20
Cache control register, 4-13
Caches
coherency and validation, 4-9
miss fetch algorithm/line fills, 4-11
CAM interface, 11-6
CCR, 2-17
Chip select
base registers, 8-3
CS0 special case, 8-2
option registers, 8-5
overview, features, usage, 8-1
registers, 8-2
Chip selects
general overview, 1-5
Clock generator, USB, 12-4
ColdFire
documentation, xlii
ColdFire core
addressing mode summary, 2-22
condition code register (CCR), 2-17
exception processing overview, 2-36
features and enhancements, 2-11
instruction set summary, 2-23
integer data formats, 2-20
programming model, 2-15
status register, 2-18
supervisor programming model, 2-18
user programming mode, 2-16
Condition code register, 2-17
Conventions
notational, xliii
terminology, xlvi
Core
version 2
overview, 1-4
D
Data
bus, 20-2
Debug
attribute trigger register, 5-7
BDM command set summary, 5-19
breakpoint operation, 5-38
Index
Index-3
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