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Table 6-5. PMR Field Descriptions (Continued)
Bits
Field
21
QSPIPDN
QSPI power-down enable. Controls the clocking to the QSPI module.
0 Clock enabled.
1 Clock disabled.
20
TIMERPDN Timer power-down enable. Controls the clocking to the timer module.
0 Clock enabled.
1 Clock disabled.
19
GPIOPDN
Parallel port power-down enable. Controls the clocking to the parallel port module.
0 Clock enabled.
1 Clock disabled.
18
USBPDN
USB power-down enable. Controls the clocking to the USB module. Clocking to the USB
module may be turned on by USD_D+ or INT1/USB_WOR, at which time this bit is
automatically cleared.
0 Clock enabled.
1 Clock disabled.
17
UART1PDN UART1 power-down enable. Controls the clocking to the UART1 module. Clocking to the
UART1 module may be restored when a change in signal level is detected on UART1RxD, at
which time this bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
16
UART0PDN UART0 power-down enable. Controls the clocking to the UART0 module. Clocking to the
UART0 module may be restored when a change in signal level is detected on UART0RxD, at
which time this bit is automatically cleared.
0 Clock enabled.
1 Clock disabled.
15-11
—
Reserved, should be cleared.
10
USBWK
USB wakeup enable. Allows clocking to the USB module to be restored when a change in
signal level is detected on USD_D+ or INT1/USB_WOR. See Table 6-6 for a description of the
interaction between the PDN and WK bits.
0 Wakeup disabled.
1 Wakeup enabled. USBPDN must also be set.
9
UART1WK
UART1 wakeup enable. Allows clocking to the UART1 module to be restored when a change in
signal level is detected on UART1RxD. See Table 6-6 for a description of the interaction
between the PDN and WK bits.
0 Wakeup disabled.
1 Wakeup enabled. UART1PDN must also be set.
8
UART0WK
UART0 wakeup enable. Allows clocking to the UART0 module to be restored when a change in
signal level is detected on UART0RxD. See Table 6-6 for a description of the interaction
between the PDN and WK bits.
0 Wakeup disabled.
1 Wakeup enabled. UART0PDN must also be set.
7-6
—
Reserved, should be cleared.
5
MOS
Main oscillator stop. Allows the MCF5272 to be put into stop mode, in which internal clocking is
stopped to the entire processor. To enter stop mode, the user must write to the ALPR and then
execute a STOP instruction. See Section 6.2.6, "Activate Low-Power Register (ALPR)." It is not
necessary to put any on-chip modules in power down mode. After setting this bit, a write
access must be made to the ALPR register to actually enter stop mode. D[31:0] are driven low,
and other bus signals are negated. Stop mode is exited when an interrupt is detected on one
the external interrupt pins, INT[6:1].
0 Stop mode disabled.
1 Stop mode enabled.
Chapter 6. System Integration Module (SIM)
Description
Programming Model
6-9
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